The molded pin-grid-array package is disclosed and claimed in U.S. Pat. No. 4,688,152 which issued to applicant on Aug. 18, 1987. This patent is also assigned to the assignee of the present invention. The basic pin-grid-array concept involves a flat semiconductor housing with a large number of package pins extending from one face thereof in an array having standard spacing. Typically, several concentric rings of pins are involved with a total pin count ranging from 28 to 172 pins.
U.S. Pat. No. 4,688,152 discloses a basic printed wiring board (PWB) that contains a plurality of plated through holes. The package pins are soldered into the holes so as to extend in an array from one face thereof. The board contains a centrally located well in which an IC chip can be mounted and the IC bonding pads are connected to printed wiring traces that interconnect with the plated through holes. The board with its mounted and connected IC chip is then located in a molding cavity which has a series of ribs that locate the board inside the mold and press the pin side of the board against the mold. The other face of the board is then covered with transfer molded plastic that encapsulates the IC chip and the surface of the board. Since the board face is pressed against the mold on the pin containing side, plastic is precluded from that side and is confined to the other side of the board. A bead of plastic exists peripherly in the form of a skirt around the edge of the board.
Where heat is generated by the IC chip, the above-described package does not remove the heat efficiently and is generally employed for housing only low power devices. The molded plastic encapsulant is not a good heat conductor and the PWB does not efficiently conduct heat. As a practical matter, most of the heat removed is by way of the package pins and, therefore, by way of the metal traces on the PWB.